1. Field of the Invention
The present invention relates to a pulse generation circuit and method for data loading in an output pre-buffer, particularly for memory devices.
2. Discussion of the Related Art
It is known that in a memory device the data present inside the memory device must, during the reading step, be transferred to output terminals of the memory device to make the data available to the outside world. Usually, the output terminals are not directly connected to the memory matrix, however, the output terminals present to the outside world the data related to the last reading operation performed on the memory device.
When a reading operation is performed, it is therefore necessary to activate the connecting path between the the memory matrix and the output terminals for data transmission.
A drawback that can often be observed is that noise, which is either present on the supply lines or generated by the switching of the memory outputs, may be superimposed on the data that has just been transmitted. Also, the noise may possess oscillatory characteristics which further interfere with the transmitted data.
When the data is loaded into an output pre-buffer, pre-buffer switches and assumes the mode dictated by the data. Once the data has been loaded into the output pre-buffer for discharge onto the output terminal, any other possible switching (not produced by an actual address transition) that occurs at the input node of the pre-buffer is associated with a new data reading operation, can undesirably alter the configuration of pre-buffer, thus corrupting the data produced by the reading operation.
By introducing an internal bus into the architecture of a memory device, a problem of determining the right moment for synchronization of the data arriving from the memory matrix, over the internal bus is created. Also, the operation of the internal bus must be transparent to external devices.